1. Field of the Invention
The present invention relates to a phase detecting circuit and a phase-locked loop (PLL) circuit.
2. Description of the Related Art
In a PLL circuit that generates a system clock signal synchronized with a reference clock signal, a phase detecting circuit generates, based on a phase difference of the system clock signal (a frequency-divided clock signal) from the reference clock signal, two control pulse signals (an UP signal and a DOWN signal) given to a charge pump circuit.
The phase detecting circuit includes a first flip-flop circuit, a data input to which is a power supply voltage and a clock input to which is the frequency-divided clock signal, a second flip-flop circuit, a data input to which is the power supply voltage and a clock input to which is the reference clock signal, and an AND circuit that generates, based on timing when an AND of data outputs of the first and second flip-flop circuits holds, a reset signal simultaneously applied to reset terminals of both the flip-flip circuits (see, for example, JP-A. 2005-51693 (KOKAI) and JP-A. 2003-209464 (KOKAI)).
Consequently, with extinction timing of the reset signal set as the end, the UP signal is output from a data output terminal of the first flip-flop circuit and the DOWN signal is output from a data output terminal of the second flip-flop circuit. The reset signal is generated with pulse width set equal to time from the timing when the AND holds until a delay time in the AND circuit elapses.
Specifically, one of the UP signal and the DOWN signal output from the two flip-flop circuits changes to a control pulse signal on an advance phase side, and pulse width on the advance phase side has time width obtained by adding the pulse width of the reset signal to time width corresponding to a phase difference between both the clock signals. The other of the UP signal and the DOWN signal changes to a control pulse signal on a delay phase side and the pulse width on the delay phase side has the pulse width of the reset signal.
As a phase detecting function of the phase detecting circuit, the pulse width of the generated two control pulse signals is desirably pulse width corresponding to the phase signal between both the clock signals on the advance phase side, and is desirably pulse width as narrow as possible on the delay phase side. Therefore, it is necessary to reduce the pulse width of the reset signal.
However, because of an operation characteristic of the flip-flop circuits, the reset signal has minimum pulse width required for the reset signal. The pulse width of the reset signal cannot be reduced to be smaller than the minimum pulse width. On the other hand, when the pulse width of the reset signal is set to the minimum pulse width, because of, for example, a fluctuation of threshold value due to use for a long time, in some case, an output reset signal is crushed and the two flip-flop circuits cannot be reset. Delay time in the AND circuit fluctuates because of the influence of an operation condition, environmental temperature, and a manufacturing process. In the configuration of the phase detecting circuit explained above, it is necessary to design the delay time in the AND circuit long to some extent such that pulse width that withstands various kinds of fluctuation and is enough for the operation of the flip-flop circuits can be obtained. Therefore, it is difficult to improve the function of the phase detecting circuit.